AI-first medical device studio · Millbrae, CA

AI-first medical device development.

one team for firmware, edge-ML, electronics, and regulatory.

One embedded team — firmware, electronics, AI/ML, and regulatory — taking you from concept to FDA clearance, with AI built into the stack, not bolted on. Startup speed, audit-ready rigor.

$ bitcron viz tplc-loop AI/ML SaMD · GMLP · PCCP
AI/ML Total Product Lifecycle (TPLC) loop A circular six-stage lifecycle — data, train, validate, deploy, monitor, update — connected by clockwise arrows. The update arrow returns to data through a PCCP gate that pre-authorizes specified model changes. Based on the FDA AI/ML SaMD Action Plan, GMLP, and the Predetermined Change Control Plan. TPLC AI / ML LOOP 01 DATA 02 TRAIN 03 VALIDATE 04 DEPLOY 05 MONITOR 06 UPDATE PCCP GATE

PCCP gate

The update path is pre-authorized: specified model changes ship without a new submission, via a Predetermined Change Control Plan.

FDA 2024 · FDORA 2022

Locked vs adaptive

We design for both — a locked algorithm, or a continuous-learning model governed inside the loop.

GMLP

10 guiding principles for Good Machine Learning Practice — FDA, Health Canada & MHRA (2021) — applied across every stage.

Source: FDA AI/ML-Based SaMD Action Plan (2021) · GMLP (FDA · Health Canada · MHRA, 2021) · Predetermined Change Control Plan (FDA final guidance, 2024).

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MOD.01 One partner, not five line items

One team beats five vendors.

Five vendors means five handoffs — and runway burned in the gaps. We own the device, the intelligence, and the submission as one accountable team.

vendors.diffusual way vs. bitcron

the usual way: five contracts, five handoffs

-firmware shop
-electronics & power consultant
-AI / ML contractor
-regulatory advisor
-systems integration vendor

the bitcron way: one accountable team

+bitcron — firmware electronics AI regulatory, one roof.
01

Full-stack, one roof

Firmware, electronics, AI/ML, and regulatory in one team. No integration tax. No finger-pointing.

02

Startup speed

Cross-discipline calls made in one room. Founder pace, with engineering that stays traceable.

03

Audit-ready from day one

Design controls and the DHF grow as you build — never reconstructed in a pre-submission panic.

04

De-risked submissions

The regulatory path is designed in from sketch one, so V&V maps clean to your 510(k) or PMA.

MOD.02 The differentiator

AI in the stack, verified for regulators.

Dropping a model into a device is easy. Proving it's safe, reproducible, and cleared to evolve is the work — and we engineer for it from the first dataset.

AI / ML engineering

Models that hold up under audit.

We own the full AI lifecycle inside the device: data pipelines, model design, on-device deployment, and the V&V evidence that makes it defensible. Regulatory thinking, in the loop from dataset one.

On-device · edge ML

Inference at the edge.

Quantized, latency-bound models that run on the target. Deterministic, and resilient when the network drops.

Edge inference

SaMD

Software as a Medical Device.

Standalone clinical software built to IEC 62304, with intended use and risk class designed in from the start.

IMDRF I–IV

Model V&V

Verification & validation.

Reproducible pipelines, dataset provenance, and performance evidence that survives reviewer scrutiny.

Traceable

FDA PCCP

AI/ML change-control plans.

Predetermined Change Control Plans that let models improve post-clearance — inside bounds the FDA already agreed to.

Modify by design

Signal processing · data pipelines

Clean signal in, trustworthy inference out.

DSP front ends, sensor fusion, and versioned pipelines: the plumbing that decides whether a model is ever trustworthy. Traceable from raw capture to the prediction it produced.

$ bitcron viz samd-categories IMDRF SaMD
Impact I → IV (highest)

Source: IMDRF, “Software as a Medical Device: Possible Framework for Risk Categorization and Corresponding Considerations.”

Why the category matters

Your SaMD category sets the depth of evidence a reviewer expects — and shapes the model, the V&V plan, and the PCCP. We place your device on the grid early, so rigor matches risk.

Lifecycle, governed

  • Locked — fixed at clearance; changes go through a new submission.
  • Adaptive — continuous-learning, governed inside the TPLC loop.
  • PCCP — modification description, modification protocol, impact assessment.

Not sure where your model lands on the grid? We'll map your SaMD category and the cleanest AI/ML path in a first call.

Talk through the pathway →
MOD.03 Where we go deep

Domains we actually build in.

Hard, regulated, high-stakes systems — where electrons, firmware, and intelligence have to work together safely.

/01

Surgical robotics

/02

Aesthetic & RF-therapy lasers

/03

Implantable neurostimulators

/04

Wireless telemetry

/05

High-power conversion electronics

/06

Precision sensing

/07

Embedded firmware

/08

iOS & app integration

MOD.04 The trust layer

Audit-ready, by construction.

We build inside the standards reviewers and notified bodies expect — so compliance is a byproduct of how we work, not a scramble at the end. The diagrams below are the frameworks we engineer to, drawn to source.

$ bitcron viz design-controls 21 CFR 820.30 / ISO 13485
FDA design controls waterfall — verification versus validation A waterfall linking user needs to the finished medical device. User needs flow down into design inputs, across the design process, to design outputs, then up to the medical device. A verification link compares design outputs to design inputs — did we build the device right. A validation link compares the medical device to user needs — did we build the right device. Design review runs throughout and all evidence is captured in the Design History File. User needs Medical device Design inputs Design outputs Design process iterative loop VALIDATION — meets user needs (did we build the RIGHT device?) VERIFICATION — outputs meet inputs (did we build the device RIGHT?) DESIGN REVIEW runs throughout · all evidence → Design History File (DHF)

Source: FDA Design Control Guidance for Medical Device Manufacturers (1997) · 21 CFR 820.30, now harmonized under FDA QMSR → ISO 13485:2016 (effective Feb 2, 2026). Verification = outputs meet inputs; validation = device meets user needs.

$ bitcron viz risk-matrix ISO 14971
ISO 14971 risk matrix — severity by probability A five by five matrix with severity of harm on the horizontal axis (negligible to catastrophic) and probability of occurrence on the vertical axis (improbable to frequent). Cell shading intensifies from mint at low risk through sky to ink at high risk. Risk equals the combination of probability and severity. SEVERITY → PROBABILITY → Frequent Probable Occasional Remote Improbable Negligible Minor Serious Critical Catastrophic

Source: ISO 14971:2019. Risk = combination of probability of harm and severity of harm. Shading uses ink-intensity with sky/mint (not red/green).

Risk management process

Analysis Evaluation Control Residual risk Review Production & post-production

Risk control priority

  1. Inherently safe design & manufacture.
  2. Protective measures in the device or manufacture.
  3. Information for safety — labeling and warnings.
$ bitcron viz v-model IEC 62304
IEC 62304 software life-cycle V-model A V-shaped diagram. The left arm decomposes from software requirements to architectural design to detailed design down to unit implementation at the vertex. The right arm integrates and tests upward from unit verification to integration testing to system testing and release. Dashed horizontal links pair each decomposition stage with its verification stage. Safety classes A, B, and C scale the rigor. Requirements Architecture Detailed design Unit implementation Unit verification Integration & testing System test & release DECOMPOSE ↘ ↗ INTEGRATE & TEST SAFETY CLASS Ano injury · Bnon-serious injury · Cdeath / serious injury

Source: IEC 62304 software life-cycle. Safety classes — A: no injury possible · B: non-serious injury possible · C: death or serious injury possible.

Also engineered to:  FDA 510(k) substantial equivalence / PMA · FDA QMSR → ISO 13485:2016 · IEC 60601 · 21 CFR 820.30 design controls → DHF · device Class I–III

MOD.05 Show the rigor

Evidence, not assertions.

Reliability and capability claims have to survive a statistician. We plan sample sizes and capability targets up front, to methods reviewers recognize — so your numbers are defensible, not hopeful.

$ bitcron viz success-run Reliability sampling
Success-run sample-size curve at 95% confidence A rising curve showing the zero-failure sample size n required versus target reliability R at 95% confidence, using n equals ln of one minus C over ln of R. Marked points: 90% reliability needs 29 units, 95% needs 59, and 99% needs 299, where the curve climbs steeply. n reliability R 0 100 200 300 .80 .90 .95 .99 n=29 n=59 n=299 n = ln(1 − C) / ln(R) · C = 95%

Source: Success-run (binomial, zero-failure) reliability. “Rule of three”: with 0 failures in n units, the 95% upper bound on the failure rate ≈ 3/n.

$ bitcron viz sample-size 95/95 family
Zero-failure sample sizes by confidence and reliability
ConfidenceReliabilityn (0 fail)
95%90%29
95%95%59
95%99%299
90%90%22

Source: success-run theorem. Acceptance sampling: ANSI/ASQ Z1.4 (attributes), Z1.9 (variables).

$ bitcron viz cpk Process capability
Process capability bell curve with spec limits A normal bell curve centered on the mean with lower and upper specification limits marked. The mint-filled area under the curve sits within the limits. Cpk of at least 1.33 corresponds to about four sigma and roughly 63 parts per million defective; Cpk of 1.00 is about three sigma. LSL USL μ Cpk ≥ 1.33 ≈ 4σ ≈ 63 ppm · Cpk = 1.00 ≈ 3σ

Source: process capability. Cpk ≥ 1.33 is a common requirement; use Ppk for process performance.

MOD.06 How we engage

Assess. Design. Validate. AI-first.

Three stages, with intelligence and the regulatory path weighed at every step — not appended at the end. Built to compress timelines and shrink submission risk.

bitcron assess

01.

Assess

Pressure-test the concept across the whole stack — where AI earns its place, where it adds risk, your likely SaMD category, and the real regulatory path.

  • Concept & gap analysis
  • AI feasibility & risk
  • Regulatory pathway map

bitcron design

02.

Design

Engineer the device, the AI, and the compliance evidence as one system — firmware, electronics, models, and the DHF in lockstep, not colliding before submission.

  • Device + electronics + firmware
  • AI/ML architecture & pipelines
  • Design controls in parallel

bitcron validate

03.

Validate

V&V to ISO/IEC, model V&V, and a complete Design History File — the work, turned into a clean, defensible submission package.

  • V&V to ISO / IEC
  • Model V&V + PCCP
  • Submission-ready DHF
Outcomes: Faster to clearance Reduced submission risk One accountable team

let's talk

Building something hard? Let's get into it.

Tell us about the device, the intelligence you want inside it, and where you're headed. No pitch deck — just engineers talking about whether we're the team to take it from concept to clearance.

Contact
Studio Millbrae, California
Status Open for new programs